The present invention relates to arbitration techniques implemented in the framework of information-processing systems.
The increasing complexity in terms of architecture of information-processing systems, and in particular of the so-called xe2x80x9cembeddedxe2x80x9d systems, renders increasingly more important the optimization of the cycles of transfer of data flow from the so-called xe2x80x9cinitiatorsxe2x80x9d to the so-called xe2x80x9ctargetsxe2x80x9d of a system.
In general, the definition of initiator applies to any unit that is able to initiate autonomously a transaction such as to involve the use of a resource (for instance, a dedicated or shared bus) in order to read or write data.
The definition of target applies to any unit starting from which or with which an initiator is able to read or write data.
A system such as an embedded system may have a large number of initiator units, as well as a large number of target units.
At the moment in which two or more initiators simultaneously endeavor to start a transaction aimed at an identical target, it is necessary to solve the conflict by means of an arbitration function. The implementation of such a function may often prove burdensome, in particular in terms of speed of execution.
FIG. 2 of the annexed drawings shows an arbitration procedure carried out according to a solution known in the art within the framework of a generic system (for example, of the embedded type), represented in FIG. 1, a figure which in itself applies both to the prior art and to the invention.
At the start of the respective transaction, each initiator I1, I2, I3, etc., presents a priority to the so-called system arbiter A, which solves the conflict by enabling start of the transactions by the initiators having the highest priority and proceeding progressively down to the ones with the lowest priority. Data transactions towards any target T are thus regulated by the arbiter A, which solves the possible conflicts by means of the priority information supplied by the initiators themselves. A transaction consists in the transfer of a data packet from the initiator involved to the target T or vice versa.
At the start of transaction, each initiator I1, I2, I3, etc., asserts a request signal to the arbiter A. The arbiter signals that the transaction has been accepted by means of a grant signal asserted to the initiator with the highest priority among the ones that wish to start the transaction simultaneously. Then it signals, in the subsequent cycles, acceptance of the transactions to the initiators having lower priorities when the transactions having higher priorities have been completed.
This procedure is shown schematically in FIG. 2 with reference to a system comprising three initiators I1, I2, I3 and a target T. The arbiter A, which operates according to the clock signal represented in the diagram at the top of FIG. 2, solves any conflicts on the basis of the priorities received with the timings shown in the FIG. All this is done by applying basically a mechanism of comparison of inequalities in sequential order, as represented in FIG. 2. Here, it is assumed that initiator I1 has a higher priority than initiator I2, which in turn has a higher priority than initiator I3, so that grants are granted in order first to initiator I1, then to initiator I2, and finally to initiator I3.
Albeit functional, the mechanism described above presents intrinsic limits related to the speed of execution of the arbitration algorithm, to the sensitivity of the speed of execution of arbitration according to the coding of the priority (typically on a generic number n of bits), and to a marked increase in the execution delay as the number of initiators increases.
An embodiment of the present invention provides a solution that is able to overcome the drawbacks referred to above.
The arbitration procedure according to an embodiment of the invention is basically a variable-priority arbitration mechanism that can be used advantageously in high-speed applications, such as in decoders for high-definition television signals. The corresponding interconnection subsystem, comprising three initiators or requesters (LMI, up-Interface, and GPx Interface units) and a target T (the SDRAM memory interface), is able to operate with a clock signal, for example, at 100 MHz. The solution makes it possible to differentiate processes having different priorities, which can access the external SDRAM through the same initiator.
In general, the solution may, however, be used in Nxc3x97M systems (i.e., with N initiators and M targets) by introducing an arbiter for each destination. The time of execution of the procedure increases only as a result of the decoding of the destination address; hencexe2x80x94referring to current technologies (such as 0.25-micron technology)xe2x80x94with values of a few tenths of nanoseconds for each destination.